Instruction Segment Sample 1
| Cycle | Instruction Segment | Current State | Next State | |||
| 1 | MEM IR <-- mem[PC] | 0 | 1 | |||
| ALU PC <-- PC + 4 | ||||||
| 2 | MEM A <-- Reg[IR[25:21]] | 1 | 2 | |||
| MEM B <-- Reg[IR[20:16]] | ||||||
| ALU ALUOut <-- PC + (SignExt(IR[15:0])<<2) | ||||||
| 3 | ALU ALUOut <-- A + SignExt(IR[15:0]) | 2 | 3 | |||
| Reg B <-- Reg[IR[20:16]] | ||||||
| 4 | MEM MDR <-- mem[ALUOut] | MEM mem[ALUOut] <-- B | 3 | 5 | 4 | 0 |
| 5 | REG Reg[IR[20:16]] <-- MDR | 4 | 0 | |||
PCWrite
PCSource=10
RegDest=10
MemtoReg=10
RegWrite